Double edge triggered flip flop power dissipation

Therefore the proposed DPDET flip-flop is suitable for low supply voltage and high speed CMOS applications. CiteSeerX - Document Details (Isaac Councill, Lee Giles, Pradeep Teregowda): Abstract- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The redundant transitions are eliminated by using the conditional technique named conditional discharge technique. Moreover, the DPDET flip-flop can be used in a 0.9V supply voltage with 224 MHz operating speed. In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. Rajesh Mehra Abstract An explicit pulsed double edge triggered sense amplifier flip-flop for the low power and low delay is presented in this paper. The power dissipation is reduced about 36 % and 29 % in compared with others for 3.3V and 2.5V supply voltage, respectively. The operating speed of the DPDET flip-flop is increased about 41 % and 49 % in compared with others for 3.3V and 2.5V supply voltage, respectively. Based on 0.35um single-poly quad-metal ' CMOS technology, the HSPICE simulation results show that the operating speed of the DPDET flip-flop is 2.7 GHz at a 3.3V supply voltage. The number of transistors is reduced by 40 % to 70 % compared to other double edge triggered flip-flops. referred to as double-edge triggered Flip-Flops otherwise it is called as single edge triggered Flip-Flops. The total transistors count is reduced to improve speed and power dissipation in flip-flop.

Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. The DPDET flip-flop uses a split output latch clocked by a short pulse train. 74LVC1G74DP - The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Clock-Gated Double-Edge Triggered Flip-Flop for Effectual Power Reduction K.Raja 1, Dr.S. In this paper, a low voltage dual-pulse-clock double edge triggered D'flip-flop (DPDET) is proposed.

Double edge triggered flip flop power dissipation